A 14-b 12-MS/s CMOS pipeline ADC with over 100-dB SFDR.

Yun Chiu Paul R. Gray Borivoje Nikolic

Published in: IEEE J. Solid State Circuits (2004)

Keyphrases

analog to digital converter
single chip
high speed
low cost
pipeline architecture
power consumption
analog vlsi
image sensor
processing pipeline
data sets
cmos image sensor
vlsi circuits
power supply
database
ibm db
low power
low voltage
rolling shutter
image processing
database manager
pac man