Efficient carry select adder using 0.12µm technology for low power applications.

A. Ramakrishna Reddy M. Parvathi

Published in: ICACCI (2013)

Keyphrases

low power
low cost
logic circuits
power consumption
high speed
cost effective
cmos technology
gate array
wireless transmission
power dissipation
single chip
vlsi circuits
vlsi architecture
real time
high power
nm technology
ultra low power
mixed signal
power reduction
model checking