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A 2.5Gb/s/pin 256Mb GDDR3 SDRAM with Series Pipelined CAS Latency Control and Dual-Loop Digital DLL.

Dong-Uk LeeHyun-Woo LeeKi Chang KweanYoung-Kyoung ChoiHyong Uk MoonSeung-Wook KwackShin-Deok KangKwan-Weon KimYong Ju KimYoung-Jung ChoiPatrick B. MoranJin-Hong AhnJoong Sik Kih
Published in: ISSCC (2006)
Keyphrases
  • feedback loop
  • data sets
  • case study
  • control system
  • high speed
  • data acquisition
  • control strategy
  • database
  • neural network
  • lower bound
  • motion estimation
  • adaptive control
  • resource utilization