A multi-level architecture for hardware Trojan and vulnerability runtime detection and response towards cryptographic IP.
Zhaojie DongLan ChenYing LiPublished in: IEICE Electron. Express (2022)
Keyphrases
- hardware architecture
- real time
- vlsi implementation
- software implementation
- hardware implementation
- vlsi architecture
- random number generator
- object detection
- hardware and software
- low cost
- multi core processors
- smart card
- multi layer
- hardware software
- software architecture
- false positives
- detection method
- detection algorithm
- embedded systems
- anomaly detection
- management system
- content addressable
- dedicated hardware
- pipeline architecture
- multithreading
- parallel architecture
- encryption scheme
- processing units
- risk assessment