A memory controller that reduces latency of cached SDRAM.
Seiji MiuraSatoru AkiyamaPublished in: ISCAS (5) (2005)
Keyphrases
- response time
- control system
- memory usage
- memory requirements
- control architecture
- dynamic model
- control algorithm
- data transfer
- real time
- memory space
- adaptive control
- memory size
- controller design
- control law
- optimal control
- closed loop
- computing power
- control scheme
- feedback control
- control strategy
- adaptive fuzzy
- robust stability