A CMOS low-power multiple 2.5-3.125-Gb/s serial link macrocellfor high IO bandwidth network ICs.
Fuji YangJay H. O'NeillDavid InglisJoseph H. OthmerPublished in: IEEE J. Solid State Circuits (2002)
Keyphrases
- low power
- high speed
- power consumption
- low cost
- communication links
- low power consumption
- single chip
- vlsi circuits
- cmos technology
- power saving
- high power
- wireless transmission
- image sensor
- energy dissipation
- logic circuits
- network resources
- digital signal processing
- gate array
- ultra low power
- delay insensitive
- real time
- peer to peer
- cmos image sensor
- low voltage
- vlsi architecture
- rate adaptation
- multicast tree
- congestion control
- digital camera
- nm technology
- sensor networks