FPGA acceleration of SAT/Max-SAT solving using variable-way cache.

Kenji Kanazawa Tsutomu Maruyama

Published in: FPL (2014)

Keyphrases

sat solving
sat solvers
boolean satisfiability
sat problem
query processing
boolean optimization
boolean formula
main memory
max sat
sat instances
orders of magnitude
sat encodings
constraint satisfaction
propositional satisfiability
simulated annealing
phase transition
symmetry breaking
data structure