Login / Signup
A 17 × 69 bit multiply and add unit with redundant binary feedback and single cycle latency.
W. S. Briggs
David W. Matula
Published in:
IEEE Symposium on Computer Arithmetic (1993)
Keyphrases
</>
gray code
binary representation
machine learning
data structure
relevance feedback
highly redundant
neural network
website
floating point
feedback loop