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A Case for Hybrid Instruction Encoding for Reducing Code Size in Embedded System-on-Chips based on RISC Processor Cores.
Govindarajalu Bakthavatsalam
K. M. Mehata
Published in:
J. Comput. Sci. (2014)
Keyphrases
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instruction set
level parallelism
processor core
instruction set architecture
high speed
floating point
application specific
multi core processors
computer architecture
address space
ibm zenterprise
parallel processing
computational complexity
real time
high end
embedded systems
operating system
multimedia