A novel formal verification approach for RTL hardware IP cores.
Ridha DjemalAyoub DhouibSamuel DellacherieRached TourkiPublished in: Comput. Stand. Interfaces (2005)
Keyphrases
- formal verification
- model checking
- multi core processors
- hardware description language
- bounded model checking
- low cost
- hardware and software
- parallel architectures
- symbolic model checking
- program slicing
- real time
- model checker
- integrated circuit
- automated verification
- computer systems
- computing systems
- processor core
- address space
- general purpose processors
- high end
- ip networks
- field programmable gate array
- model based diagnosis
- hardware implementation
- temporal logic
- programmable logic
- computing power