A coherent hybrid SRAM and STT-RAM L1 cache architecture for shared memory multicores.
Jianxing WangYenni TimWeng-Fai WongZhong-Liang OngZhenyu SunHai LiPublished in: ASP-DAC (2014)
Keyphrases
- memory access
- shared memory
- random access memory
- multi processor
- parallel algorithm
- message passing
- multithreading
- parallel computing
- distributed memory
- parallel architecture
- shared memory multiprocessors
- instruction set
- parallel tree search
- memory management
- parallel machines
- parallel architectures
- data access
- main memory
- parallel programming
- parallel computation
- shared memory multiprocessor
- power consumption
- embedded dram
- graphic processing unit
- parallel computers
- real time
- external memory
- address space