Model checking SystemC designs using timed automata.
Paula HerberJoachim FellmuthSabine GlesnerPublished in: CODES+ISSS (2008)
Keyphrases
- timed automata
- model checking
- temporal logic
- reachability analysis
- temporal properties
- formal verification
- formal specification
- model checker
- finite state
- partial order reduction
- automated verification
- verification method
- finite state machines
- computation tree logic
- process algebra
- epistemic logic
- symbolic model checking
- transition systems
- bounded model checking
- formal methods
- concurrent systems
- asynchronous circuits
- satisfiability problem
- reactive systems
- pspace complete