A novel architecture for LZSS compression of configuration bitstreams within FPGA.
Radek IsaJirí MatousekPublished in: DDECS (2017)
Keyphrases
- hardware implementation
- hardware architecture
- software implementation
- hardware design
- real time
- fpga implementation
- fpga technology
- compression algorithm
- management system
- hardware architectures
- dedicated hardware
- compression ratio
- parallel architecture
- high speed
- xilinx virtex
- field programmable gate array
- bitstream
- image compression
- compression scheme
- data compression
- fpga device
- pipelined architecture
- reconfigurable hardware
- video signals
- random access
- signal processing
- low cost
- image sequences