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On Accelerating SMT-based Bounded Model Checking of HSTM Designs.
Weiqiang Kong
Leyuan Liu
Yoriyuki Yamagata
Kenji Taguchi
Hitoshi Ohsaki
Akira Fukuda
Published in:
APSEC (2012)
Keyphrases
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bounded model checking
model checking
formal verification
temporal logic
linear temporal logic
multi agent systems
statistical machine translation
cooperative
information retrieval
learning algorithm
finite state
description language