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Novel Design partitioning technique for ASIC prototyping on multi-FPGA platforms using Graph Deep Learning.
Divyasree Tummalapalli
Kunapareddy Chiranjeevi
Vikas Akalwadi
Rahul Govindan
Balaji G
Published in:
ICECS 2022 (2022)
Keyphrases
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deep learning
design process
single chip
hardware architecture
design methodology
unsupervised learning
hardware implementation
co occurrence
learning algorithm
high dimensional
signal processing
maximum likelihood
long range
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