Implementation of DDR3 SDRAM multi-channel read and write circuit based on FPGA.
Zhishuo WangDongming XuYuhao LiPublished in: AIPR (2023)
Keyphrases
- multi channel
- high speed
- hardware implementation
- single channel
- anti aliasing
- hardware design
- circuit design
- mixed signal
- signal processing
- efficient implementation
- hardware description language
- hardware architecture
- read write
- fpga technology
- mobile devices
- hardware architectures
- reconfigurable hardware
- field programmable gate array
- low cost
- multiresolution