C
search
search
reviewers
reviewers
feeds
feeds
assignments
assignments
settings
logout
Modeling of 10-bits, 40 MHz, low power pipelined ADC utilizing novel background calibration.
Jiri Haze
Lukas Fujcik
Ondrej Sajdl
Radimir Vrba
Published in:
ICN/ICONS/MCL (2006)
Keyphrases
</>
low power
high speed
power consumption
single chip
low cost
cmos technology
wireless transmission
vlsi architecture
digital signal processing
nm technology
high power
logic circuits
image sensor
real time
data flow
infrared
digital camera
delay insensitive
image compression