A low-power programmable DSP core architecture for 3G mobile terminals.
Takahiro KumuraDaiji IshiiMasao IkekawaIchiro KurodaMakoto YoshidaPublished in: ICASSP (2001)
Keyphrases
- low power
- digital signal processing
- low cost
- signal processor
- high speed
- single chip
- vlsi architecture
- mobile terminals
- power consumption
- low power consumption
- digital signal processors
- signal processing
- cmos technology
- nm technology
- vlsi circuits
- data flow
- real time
- mixed signal
- gate array
- logic circuits
- cost effective
- vlsi implementation
- personal computer
- data exchange
- data processing
- power reduction
- wireless communication
- query processing
- data streams