A process variation tolerant, high-speed and low-power current mode signaling scheme for on-chip interconnects.
Marshnil Vipin DaveMaryam Shojaei BaghiniDinesh Kumar SharmaPublished in: ACM Great Lakes Symposium on VLSI (2009)
Keyphrases
- high speed
- low power
- cmos technology
- low cost
- single chip
- power dissipation
- low power consumption
- power consumption
- high power
- mixed signal
- low voltage
- signal processor
- logic circuits
- wireless transmission
- real time
- gate array
- vlsi architecture
- power reduction
- image sensor
- energy efficiency
- cmos image sensor
- design process
- nm technology