Schnelle Berechnung von 2D-FIR-Filteroperationen mittels FPGA-Koprozessor microEnable.
Stefan HezelReinhard MännerPublished in: DAGM-Symposium (1999)
Keyphrases
- field programmable gate array
- filter bank
- filter design
- high speed
- hardware implementation
- real time image processing
- iir filters
- signal processing
- finite impulse response
- verilog hdl
- digital filters
- digital signal
- hardware design
- low cost
- systolic array
- real time
- hardware architectures
- software implementation
- fir filters
- hardware architecture
- low pass filter
- information systems
- fpga technology
- pipelined architecture
- data sets
- parallel architecture
- fpga implementation
- single chip
- low pass
- data acquisition
- xilinx virtex
- frequency domain
- pattern recognition
- fpga hardware
- gate array