Central Limit Model Checking.
Luca BortolussiLuca CardelliMarta KwiatkowskaLuca LaurentiPublished in: ACM Trans. Comput. Log. (2019)
Keyphrases
- model checking
- temporal logic
- automated verification
- temporal properties
- reachability analysis
- formal verification
- finite state machines
- formal specification
- finite state
- symbolic model checking
- verification method
- partial order reduction
- model checker
- epistemic logic
- bounded model checking
- transition systems
- computation tree logic
- formal methods
- timed automata
- process algebra
- pspace complete
- concurrent systems
- reactive systems
- artificial intelligence
- satisfiability problem
- asynchronous circuits
- abstract interpretation
- ordered binary decision diagrams
- deterministic finite automaton