Impact of Circuit Degradation on FPGA Design Security.

Han-Wei Chen Suresh Srinivasan Yuan Xie Vijaykrishnan Narayanan

Published in: ISVLSI (2011)

Keyphrases

circuit design
gate array
high speed
functional requirements
verilog hdl
case study
design process
low power
real time
design methodology
electronic circuits
programmable logic
hardware architecture
hardware design
information security
access control
neural network