A Hybrid Reconfigurable Cluster-on-Chip Architecture With Message Passing Interface For Image Processing Applications.
Irfan SyedJohn A. WilliamsNeil W. BergmannPublished in: FPL (2007)
Keyphrases
- reconfigurable hardware
- image processing
- low cost
- message passing interface
- field programmable gate array
- hardware implementation
- management system
- functional units
- high speed
- multithreading
- signal processing
- massively parallel
- parallel implementation
- image processing algorithms
- real time
- processing units
- message passing
- parallel algorithm
- hardware design
- low power
- high performance computing
- parallel architectures
- image segmentation
- parallel computing
- distributed systems
- cmos technology
- general purpose
- query processing