A composite sub-optimal approach for hardware implementation of turbo decoder.
Vanukuru Hari RohitAkshay SharmaNigar ShajiPublished in: ICC (2013)
Keyphrases
- hardware implementation
- fpga implementation
- software implementation
- signal processing
- efficient implementation
- hardware architecture
- image processing algorithms
- hardware design
- field programmable gate array
- error concealment
- parallel architecture
- dedicated hardware
- pipeline architecture
- real time
- machine learning
- low complexity