A 53-Gbit/s Optical Receiver Frontend With 0.65 pJ/bit in 28-nm Bulk-CMOS.
László SzilágyiJan PlívaRonny HenkerDavid SchoenigerJaroslaw P. TurkiewiczFrank EllingerPublished in: IEEE J. Solid State Circuits (2019)
Keyphrases
- nm technology
- random access memory
- cmos technology
- power consumption
- silicon on insulator
- focal plane
- analog to digital converter
- low power
- image sensor
- metal oxide semiconductor
- high speed
- back end
- imaging systems
- power dissipation
- low cost
- analog vlsi
- design considerations
- delay insensitive
- low voltage
- solid state
- power supply
- optical properties
- atmospheric turbulence
- font recognition
- infrared