Instruction flow-based front-end throttling for power-aware high-performance processors.
Amirali BaniasadiAndreas MoshovosPublished in: ISLPED (2001)
Keyphrases
- instruction set
- embedded processors
- signal processor
- back end
- multithreading
- distributed memory
- parallel processing
- parallel computers
- memory subsystem
- power consumption
- multimedia
- highly parallel
- parallel algorithm
- single chip
- high efficiency
- instructional design
- shared memory
- flow field
- signal processing
- pc cluster
- memory hierarchy
- data management
- general purpose
- e learning