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On the Impact of Replacing Low-Speed Configuration Buses on FPGAs with the Chip's Internal Configuration Infrastructure.

Karel HeyseJente BasteleusBrahim Al FarisiDirk StroobandtOliver KadlcekOliver Pell
Published in: ACM Trans. Reconfigurable Technol. Syst. (2015)
Keyphrases
  • low cost
  • high speed
  • real time
  • data sets
  • neural network
  • parallel processing
  • single chip
  • optimal configuration