Login / Signup
Hardware-Efficient Node Processing Unit Architectures for Flexible LDPC Decoder Implementations.
Peter Hailes
Lei Xu
Robert G. Maunder
Bashir M. Al-Hashimi
Lajos Hanzo
Published in:
IEEE Trans. Circuits Syst. II Express Briefs (2018)
Keyphrases
</>
processing units
parallel architectures
parallel processing
efficient implementation
parallel computing
ldpc codes
computing systems
general purpose
data management
software systems
low complexity
distributed source coding