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An ultra-low power multiplier using multi-valued adiabatic logic in 65 nm CMOS process.
Yuejun Zhang
Dailu Ding
Zhao Pan
Pengjun Wang
Qiaoyan Yu
Published in:
Microelectron. J. (2018)
Keyphrases
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multi valued
ultra low power
single valued
truth values
multiple valued
logic synthesis
low power
boolean functions
normal form
lower bound
power consumption
hardware implementation
cmos technology