A 1.2V CMOS multiplier for 10 Gbit/s equalization.
Justin P. AbbottCalvin PlettJohn W. M. RogersPublished in: ESSCIRC (2005)
Keyphrases
- high speed
- power consumption
- floating point
- low cost
- circuit design
- low power
- hardware implementation
- power supply
- analog vlsi
- contrast enhancement
- vlsi circuits
- type ii
- low voltage
- delay insensitive
- multipath
- image sensor
- decision feedback
- cmos image sensor
- efficient implementation
- random access memory
- cmos technology
- solid state
- single chip
- data sets
- signal processing