Design of CMOS 5 Gb/s 4-PAM transceiver frontend for low-power memory interface.
Woo-Rham BaeByoung-Joo YooDeog-Kyoon JeongPublished in: ISOCC (2012)
Keyphrases
- low power
- ultra low power
- high speed
- single chip
- power consumption
- power dissipation
- low cost
- low power consumption
- cmos technology
- vlsi architecture
- logic circuits
- digital signal processing
- gate array
- wireless transmission
- mixed signal
- user interface
- nm technology
- high power
- vlsi circuits
- power reduction
- analog to digital converter
- cmos image sensor
- low voltage
- delay insensitive
- real time
- low complexity
- image sensor
- data management