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A Bin-by-Bin Calibration with Neural Network for FPGA-Based Tapped-Delay-Line Time-to-Digital Converter.

Yue XuJie XieZhiwei XingWenqiang YuanGuanqun YuZhongmin ZengBaoshun ZhangDongmin Wu
Published in: RCAR (2022)
Keyphrases