Login / Signup

A Bin-by-Bin Calibration with Neural Network for FPGA-Based Tapped-Delay-Line Time-to-Digital Converter.

Yue XuJie XieZhiwei XingWenqiang YuanGuanqun YuZhongmin ZengBaoshun ZhangDongmin Wu
Published in: RCAR (2022)
Keyphrases