Pipeline Scheduling with Dual Voltages for Low Power Design.

Chaeseok Lim Jong Tae Kim

Published in: CDES (2007)

Keyphrases

low power
power consumption
low cost
single chip
high speed
low power consumption
vlsi architecture
cmos technology
power dissipation
logic circuits
power reduction
gate array
vlsi circuits
wireless transmission
mixed signal
digital signal processing
high power
scheduling algorithm
motion estimation
real time