A 32-Gb/s 0.46-pJ/bit PAM4 CDR Using a Quarter-Rate Linear Phase Detector and a Low-Power Multiphase Clock Generator.
Zhao ZhangGuang ZhuCan WangLi WangC. Patrick YuePublished in: A-SSCC (2019)
Keyphrases
- low power
- high speed
- power consumption
- low cost
- single chip
- piecewise constant
- high power
- vlsi circuits
- digital signal processing
- energy dissipation
- power reduction
- vlsi architecture
- low power consumption
- level set
- wireless transmission
- real time
- mixed signal
- power dissipation
- logic circuits
- power saving
- gate array
- level set method
- cmos technology
- image processing