Algorithm/Hardware Co-Design Configurable SAR ADC with Low Power for Computing-in-Memory in 28nm CMOS.

Zhiwang Guo Deyang Chen Xiaoyong Xue

Published in: ASICON (2021)

Keyphrases

low power
low cost
power consumption
single chip
high speed
vlsi architecture
digital signal processing
vlsi circuits
computational complexity
wireless transmission
power reduction
image sensor
cmos technology
image processing algorithms
high power
real time
computing systems
hardware implementation
image processing