Automatic generation of synthesizable hardware implementation from high level RVC-cal description.
Khaled JerbiMickaël RauletOlivier DéforgesMohamed AbidPublished in: ICASSP (2012)
Keyphrases
- hardware implementation
- high level
- field programmable gate array
- low level
- signal processing
- efficient implementation
- hardware architecture
- hardware design
- dedicated hardware
- image processing algorithms
- fpga implementation
- automatically generate
- software implementation
- memory management
- pipeline architecture
- neural network
- fpga device
- pattern recognition
- embedded systems
- source code
- high speed