CNN Accelerator with Minimal On-Chip Memory Based on Hierarchical Array.
Hyun-Wook SonYongSeok NaTaeHyun KimAli A. Al-HamidHyungWon KimPublished in: ISOCC (2021)
Keyphrases
- programmable logic
- high speed
- cellular neural networks
- field programmable gate array
- hierarchical model
- focal plane
- low cost
- parallel implementation
- analog vlsi
- random access memory
- hierarchical structure
- machine learning
- coarse to fine
- image sensor
- single chip
- physical design
- hidden markov models
- neural network
- database