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Low Power Design Technique in Passive Tag to Reduce the EMD Noise for Reliable Communication with Reader.
Rahul Pathak
Raghavendra Kongari
Shankar Joshi
Published in:
VLSI Design (2019)
Keyphrases
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low power
single chip
power consumption
low power consumption
low cost
high speed
logic circuits
vlsi architecture
gate array
digital signal processing
power dissipation
vlsi circuits
ultra low power
real time
signal processor
rfid reader
power reduction
design process
signal processing
image processing