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Efficient Multiplier for pairings over Barreto-Naehrig Curves on Virtex-6 FPGA.
Riadh Brinci
Walid Khmiri
Mefteh Mbarek
Abdellatif Ben Rabaa
Ammar Bouallegue
Faouzi Chekir
Published in:
IACR Cryptol. ePrint Arch. (2013)
Keyphrases
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hardware implementation
field programmable gate array
real time
computationally efficient
efficient implementation
database
data sets
data structure
pattern recognition
high speed
signal processing
lightweight
b spline
parallel algorithm
computationally expensive
floating point