Energy efficient low-power full-adder by 65 nm CMOS technology in ALU.
N. Suresh KumarParamasivam KPublished in: Concurr. Comput. Pract. Exp. (2019)
Keyphrases
- cmos technology
- energy efficient
- low power
- power dissipation
- power consumption
- energy efficiency
- logic circuits
- wireless sensor networks
- high speed
- low cost
- energy consumption
- low voltage
- sensor networks
- single chip
- floating point
- digital signal processing
- power management
- mixed signal
- low power consumption
- silicon on insulator
- energy saving
- base station
- image processing
- sensor nodes
- image sensor
- data center
- coding scheme
- routing protocol
- real time