Noise estimation due to signal activity for capacitively coupled CMOS logic gates.
Kevin T. TangEby G. FriedmanPublished in: ACM Great Lakes Symposium on VLSI (2000)
Keyphrases
- noise estimation
- logic circuits
- delay insensitive
- noise level
- noisy images
- denoising
- additive noise
- low power
- signal processing
- power consumption
- wyner ziv video coding
- noise variance
- frequency domain
- chip design
- denoising methods
- action potentials
- random access memory
- high frequency
- non stationary
- high speed
- power supply
- wavelet packet
- wiener filter
- image deblurring
- noise reduction
- higher order
- multiscale