Low-voltage on-chip cache architecture using heterogeneous cell sizes for high-performance processors.
Hamid Reza GhasemiStark C. DraperNam Sung KimPublished in: HPCA (2011)
Keyphrases
- low voltage
- embedded dram
- random access memory
- multithreading
- cmos technology
- embedded processors
- signal processor
- single chip
- memory subsystem
- low power
- memory access
- design considerations
- parallel processing
- distributed memory
- signal processing
- mixed signal
- memory hierarchy
- parallel computing
- low cost
- high speed
- instruction set
- power line
- image sensor
- power consumption
- parallel computers
- parallel implementation
- cache misses
- data access
- main memory
- parallel algorithm
- shared memory
- level parallelism
- data flow
- processor core
- ibm zenterprise
- power dissipation
- memory management