An optimized hardware architecture for intra prediction in H.264 decoder.
Qi WangQuanquan LiShi ChenTiejun ZhangChaohuan HouPublished in: ASICON (2013)
Keyphrases
- hardware architecture
- intra prediction
- avc intra
- video coding standard
- mode decision
- coding efficiency
- hardware implementation
- low complexity
- video coding
- video compression
- coding method
- rate distortion optimized
- digital video
- video codec
- spatial correlation
- motion vectors
- pixel wise
- video transmission
- motion compensated
- motion compensation
- motion estimation
- rate distortion
- macroblock
- discrete cosine transform
- error concealment
- associative memory
- image coding
- block size
- distributed video coding
- intra coding
- mode selection
- image compression
- image processing
- efficient implementation
- field programmable gate array
- bit rate
- pattern recognition