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A scalable hash scheduler for decoding of multiple H.264/AVC streams on multi-core architecture.

Dung VuJilong KuangLaxmi N. Bhuyan
Published in: ICME (2014)
Keyphrases
  • multi core architecture
  • energy efficient
  • multi core processors
  • decoding process
  • data streams
  • video coding
  • low complexity
  • video codec
  • digital signal processor