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A high-performance framework for a network programmable packet processor using P4 and FPGA.

Abbas YazdinejadReza M. PariziAli BohlooliAli DehghantanhaKim-Kwang Raymond Choo
Published in: J. Netw. Comput. Appl. (2020)
Keyphrases
  • single chip
  • low cost
  • high speed
  • computer networks
  • network traffic
  • hardware implementation
  • internet traffic