Login / Signup

Optimal placement of vertical connections in 3D Network-on-Chip.

Thomas Canhao XuGert SchleyPasi LiljebergMartin RadetzkiJuha PlosilaHannu Tenhunen
Published in: J. Syst. Archit. (2013)
Keyphrases
  • optimal placement
  • network on chip
  • routing algorithm
  • multi processor
  • network simulator
  • optimal location
  • data transfer
  • interconnection networks
  • response time
  • genetic programming
  • cmos technology