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A novel SEU, MBU and SHE handling strategy for Xilinx Virtex-4 FPGAs.
Xabier Iturbe
Mikel Azkarate-askasua
Imanol Martinez
Jon Pérez
Armando Astarloa
Published in:
FPL (2009)
Keyphrases
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field programmable gate array
xilinx virtex
hardware implementation
embedded systems
parallel computing
image processing algorithms
hardware architecture
computer vision
data management
efficient implementation