Write Avoidance Cache Coherence Protocol for Non-volatile Memory as Last-Level Cache in Chip-Multiprocessor.
Ju Hee ChoiJong Wook KwakChu Shik JhonPublished in: IEICE Trans. Inf. Syst. (2014)
Keyphrases
- main memory
- multithreading
- memory subsystem
- memory access
- level parallelism
- cache conscious
- memory hierarchy
- read write
- processor core
- data access
- random access memory
- buffer pool
- speculative execution
- data structure
- memory bandwidth
- low cost
- cache misses
- secondary storage
- data storage
- external memory
- flash memory
- parallel computing
- scheduling algorithm
- database management systems
- single chip
- hit rate
- computational power
- shared memory
- prefetching
- memory requirements
- data management