A 81nW Error Amplifier Design for Ultra Low Leakage Retention Mode Operation of 4Mb SRAM Array in 40nm LSTP Technology.

Ankush Mamgain Anuj Grover

Published in: SoCC (2018)

Keyphrases

cmos technology
case study
long term
power consumption
engineering design
interaction design
high sensitivity
enabling technology
data processing
design process
cost effective
times faster
programmable logic