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A Low-Latency FPGA Accelerator for YOLOv3-Tiny With Flexible Layerwise Mapping and Dataflow.
Minsik Kim
Kyoungseok Oh
Youngmock Cho
Hojin Seo
Xuan Truong Nguyen
Hyuk-Jae Lee
Published in:
IEEE Trans. Circuits Syst. I Regul. Pap. (2024)
Keyphrases
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low latency
high speed
field programmable gate array
highly efficient
parallel computing
high bandwidth
real time
high throughput
virtual machine
massive scale
hardware implementation
low cost
data flow
stream processing
data acquisition
mobile nodes
embedded systems
data processing